1. Priority Claim
This application claims the benefit of priority from Korean Application No. 2006-0034612 filed on Apr. 17, 2006, which is incorporated herein by reference.
2. Technical Field
The present invention relates to a display device and a method of driving a display device.
3. Related Art
In a liquid crystal display a liquid crystal material with an anisotropic dielectric constant is formed between an upper transparent insulating substrate and a lower transparent insulating substrate. Molecular arrangement of the liquid crystal material is changed by the intensity of the electric field applied to the liquid crystal material such that the amount of light transmitted through the transparent insulating substrates may be controlled, and thereby display a desired image. In the liquid crystal display, a thin film transistor liquid crystal display (TFT LCD) using a TFT as a switching device is generally used.
In FIG. 1 the liquid crystal display has a display panel 100, a gate driver 110, a data driver 120, a timing controller 130 and a gamma voltage supplier 140. The display panel 100 has a plurality of pixels formed at regions where gate lines GL1, GL2, . . . , and GLn and data lines DL1, DL2, . . . , and DLm intersect each other. The gate lines are arranged in a first direction, and the data lines are arranged in a second direction substantially perpendicular to the first direction. Thin film transistors respectively having a gate electrode, a source electrode, and a drain electrode arranged in regions where the gate lines and the data lines intersect. A liquid crystal capacitor Clc and a storage capacitor Cst are arranged in the respective pixel P. The liquid crystal capacitor Clc may be equivalent to a liquid crystal material. The storage capacitor Cst maintains voltage stored in the liquid crystal cell Clc.
The respective pixel P of the panel 100 displays an image based on scan signals provided through the gate lines GL1, GL2, . . . , and GLn and data signals provided through the data lines DL1, DL2, . . . , and DLm. A scan signal may represent a pulse having a gate high voltage supplied only during one horizontal period and a gate low voltage supplied during the remnant period. The thin film transistor of each pixel P is turned on when the gate high voltage is applied thereto, so that the data signals from the data line DL1, DL2, . . . , DLm are provided to the liquid crystal cells Clc through the turned-on thin film transistor TFT. Furthermore, when the gate low voltage from the gate line GL1, GL2, . . . , GLn is applied, the thin film transistor is turned off so that the data signal stored in the liquid crystal cell Clc is maintained.
The gate driver 110 sequentially provides a plurality of scan signals to the gate lines GL1, GL2, . . . , and GLn in response to the gate control signal from the timing controller 130. The data driver 120 transforms red pixel data, green pixel data and blue pixel data into data voltages in response to the data control signal from the timing controller 130, and supplies the data voltages to the data line DL1, DL2, . . . , and DLm. The data voltage may represent a gamma voltage, which is selected among the gamma voltages supplied from the gamma voltage supplier 140, corresponding to the red, green and blue pixel data (e.g., gray levels).
The timing controller 130 generates the gate control signals for controlling the gate driver 110 and the data control signals for controlling the data driver 120 based on the externally provided red, green and blue pixel data, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a clock CLK. The gate control signals have a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, etc. The data control signals have a source start pulse SSP, a source output enable signal /SOE, a polarity control signal POL, etc. The gamma voltage supplier 140 generates the gamma voltages, which corresponds to respective gray levels, and supplies the generated gamma voltages to the data driver 120. The gamma voltages are used for digital-to-analog conversion at the data driver 120.
When the panel 100 is driven, an inversion driving method is used to prevent degradation of the liquid crystal material, which inverses a polarity of the pixel. The inversion driving method is divided into a frame inversion method, a column inversion method and a dot inversion method. The inversion driving method has disadvantage that power consumption increases because of the periodic inversion of the polarity of the data voltage. Thus, a charge sharing method is used together with the inversion driving method to solve the disadvantage of the power consumption.
FIG. 2A is a schematic showing multiple switches, and FIG. 2B is a timing diagram showing of the charge sharing method. In the charge sharing method, data lines DL1, . . . , DLm receive voltages of which voltage level is between a data voltage of a positive polarity and a data voltage of a negative polarity, so that variation range of the voltage at the data lines DL1, . . . , DLm may not be too large.
In FIGS. 1 and 2B, the source output enable signal /SOE and the polarity control signal POL are transmitted from the timing controller 130 to the data driver 130. DP denotes a waveform of the data voltage outputted from the data driver 120 to the data lines DL1, . . . , DLm. At the low level period of the source output enable signal /SOE, switches SW1 of FIG. 2A are turned on, and data voltages of a positive polarity are supplied to the data lines DL1, . . . , DLm such that panel 100 displays a predetermined image corresponding to the data voltages. At the high level period of the source output enable signal /SOE, switches SW2 of FIG. 2A are turned on, the data lines DL1, . . . , DLm are electrically connected to each other, so that the data lines DL1, . . . , DLm have an average level of the voltages supplied to the data lines DL1, . . . , DLm during the low level period of the previous source output enable signal /SOE. Hence, the data lines DL1, . . . , DLm have a voltage level between the data voltage of the positive polarity and the data voltage of the negative polarity.
Afterwards, when the high level period of the source output enable signal /SOE is changed to the low level period of the source output enable signal /SOE, the data voltages of the negative polarity are applied to the data lines DL1, . . . , DLm such that the panel 100 displays an image corresponding to the data voltages. Variation in the range of the voltages at the data lines DL1, . . . , DLm may be minimized because the voltages of the data line DL1, . . . , DLm have a voltage level that lies between the data voltage of the positive polarity and the data voltage of the negative polarity. Thus, the power consumption may be diminished.
After the panel 100 displays the image according to the data voltages of the negative polarity, the source output enable signal /SOE is changed to the high level. In case that the source output enable signal /SOE is changed to the high level, the data lines DL1, . . . , DLm have the average level of the voltages supplied to the data lines DL1, . . . , DLm during previous period (the low level period of the source output enable signal /SOE). Hence, the data lines DL1, . . . , DLm maintain a voltage between the data voltage of the positive and the data voltage of the negative signal.
In some charge sharing methods, the source output enable signal /SOE has a period during which the charge sharing is performed and a period during which the data voltages are provided to the data lines DL1, . . . , DLm. The time period during which the data voltages are applied to the data lines DL1, . . . , DLm is related with the image shown in the panel 100, ghost image, charging characteristics of the liquid crystal cell Clc, the generation of the heat at the data driver 120, and operation characteristics.
Therefore, some charge sharing methods may not provide an effective charge sharing method when the pulse width of the source output enable signal /SOE is fixed regardless of some factors (ghost image, charging characteristics of the liquid crystal cell Clc, the generation of the heat at the data driver 120, and operation characteristics, etc).